In order to decrease costs and/or improve performance it is desirable to provide semiconductor devices with more densely spaced structures. State of the art semiconductor elements can be formed with dimensions of about 0.15 μm. Such a minimum design rule is typical for state of the art semiconductor devices, such as memory devices and logic devices that are currently in research and development.
Miniaturization is an effective means of achieving a semiconductor device having improved high performance and multiple functions. Through a high level of integration, the speed of semiconductor devices may be improved and more components may be placed on a semiconductor device, thus improving functional capabilities. Thus, increasing the level of integration is essential for future semiconductor device manufacturing. In order to increase the level of integration, a trench filled with an insulating material can be used to electrically separate semiconductor elements. The use of a trench filled with an insulating material was proposed more than 20 years ago and was first applied to bipolar transistors although currently it has been applied to semiconductor devices having metal oxide semiconductor (MOS) transistors.
When a trench filled with an insulating material is used to separate MOS transistors, a hump phenomenon can occur in the sub-threshold current characteristics. This will now be explained with reference to FIG. 9. Referring to FIG. 9, a graph illustrating the relationship between the source-drain current and the gate voltage of a MOS transistor is set forth. The current characteristics of a MOS transistor operating in an intended manner is illustrated by solid line B. The dashed line A illustrates an abnormal current in the sub-threshold region that can occur in a MOS transistor that is isolated with a trench filled with an insulating layer. The dashed line A becomes the same as the intended operation (solid line B) when the MOS transistor is fully turned on. The sub-threshold current bulge illustrated by the dashed line A, which appears in the source-drain current—gate voltage characteristics illustrated in FIG. 9, is called a hump.
When the hump phenomenon occurs, the threshold value of the MOS transistor can become smaller than the designed value. Also, the reliability of the gate insulation film of the MOS transistor may be reduced, so that more semiconductor devices become defective and yield decreases. The hump can be caused by the top section of the trench developing sharp corners and a deep cavity occurring in the insulating material filling the trench.
Various methods have been proposed to solve the above-mentioned hump characteristic. One example is described in Japanese Unexamined Patent Application, First Publication no. 2000-049222 (JPA-049222). The conventional approach described in JPA-049222 will now be described with reference to FIG. 10(a)-(d).
Referring now to FIG. 10(a)-(d), cross sectional views of a conventional trench element separation region after various processing steps is set forth. The reference numerals used may not be the same as the reference numerals used in JPA-049222.
As illustrated in FIG. 10(a), a trench 104 is formed in a predetermined region of a silicon substrate 101. The trench 104 is formed by dry etching while using a pad oxide film 102 and a silicon nitride film 103, which are patterned, as an etching mask. Then, the exposed sections of the pad oxide film 102 are etched to form recessed sections 105.
Next, as illustrated in FIG. 10(b), the surface of trench 104 exposed is isotropically etched to round off the corners of the trench top section, thus producing rounded corners 106. Then, thermal oxidation is performed to form a liner oxide film 107 on the inner surface of trench 104. In this case, the liner oxide film 107 is integrated with the pad oxide film 102. Then, a filling insulation film 108 is deposited all over by a chemical vapor deposition (CVD) method such that silicon nitride film 103 is covered and trench 104 is filled.
Next, the filling insulation film 108 is polished by a standard chemical mechanical polishing (CMP) method using the silicon nitride film 103 as a polishing stopper. The result, as illustrated in illustrated in FIG. 10(c), is that a trench element separation insulating material 109 fills the trench 104.
Next, as illustrated in FIG. 10(d), silicon nitride film 103 and pad oxide film 102 are removed by etching. In this way, the sharp corners on the top section of the trench 104 are rounded. A trench element separation region, which is filled with liner oxide film 107 and trench element separation insulating material 109, is formed in the trench 104 in a predetermined region of the silicon substrate 101. Referring back to FIG. 10(c), silicon nitride film 103 can have an overhang occupying space at the edges of the trench 104. The trench element separation insulating material 109 can not fill the trench 104 at the space occupied by the overhang in the formed silicon nitride film 103. Thus as illustrated in FIG. 10(d), cavities (110 and 110a) are easily formed at the edges of trench element separation insulating material 109.
Through subsequent processes (not shown), a gate insulating film is formed. A gate electrode is then formed over the gate insulating film. In this manner, a MOS transistor is formed and isolated by using the trench element separation region.
A number of techniques have been disclosed to prevent cavities from occurring at the edges of the trench element separation insulation material. One technique is a method described in U.S. Pat. No. 5,981,356 (U.S. Pat. No. 5,981,356) where, in the formation of the trench element insulation material, a pullback process for slightly etching the surface of the silicon nitride is added after the liner oxide film formation process and before the filling insulation film is formed.
The conventional technique disclosed in U.S. Pat. No. 5,981,356 will now be described with reference to FIGS. 11(a)-(c) and FIGS. 12(a)-(c).
Referring now to FIGS. 11(a)-(c) and FIGS. 12(a)-(c), cross-sectional views of a conventional trench element separation region after various processing steps is set forth. The reference numerals used may not be the same as the reference numerals used in U.S. Pat. No. 5,981,356.
As illustrated in FIG. 11(a), a pad oxide film 202 and a silicon nitride film 203 are patterned in a predetermined region of a silicon substrate 201 and used as an etching mask. In this way, a trench 204 is formed by dry etching. Then a liner oxide film 205 is formed on the inner surface of the trench 204. In this case, the liner oxide film 205 is integrated with the pad oxide film 202 by thermal oxidation.
As illustrated in FIG. 11(b), the semiconductor device is immersed in a phosphoric acid solution thereby etching the surface of the silicon nitride film 203 and a silicon nitride film 203a is formed. The step of etching the silicon nitride film 203 is called a pullback process. Edges 206 of the silicon nitride film 203a move backward from the top sections of the trench and leave the formation region of the liner oxide film 205.
Next, as illustrated in FIG. 11(c), the filling insulation film 207 is deposited all over such that the silicon nitride film 203a is covered and the trench 204 is filled.
Then, as illustrated in FIG. 12(a), the filling insulation film 207 is polished by the CMP method using the silicon nitride film 203 as a polishing stopper so that a trench element separation insulating material 208 fills the trench.
Next, as illustrated in FIG. 12(b), the silicon nitride film 203a is removed by etching. Then, the surface of trench element separation insulating material 208 is reshaped by argon sputtering or the like to form a smooth trench element separation insulating material 208a. The thickness of the pad oxide film 202 is thinned by the abovementioned process to form a pad oxide film 202a. In this case, the liner oxide film 205 is protected by the trench element separation insulating material 208a, so that it is not etched by the abovementioned process. In the conventional example illustrated in U.S. Pat. No. 5,981,356, the trench element separation insulating material 208c extends beyond the top section of the trench 204 because the edges 206 of the silicon nitride film 203a were moved backward from the top section of the trench in the pullback process. The extension of the trench element separation insulating material 208c beyond the top section of the trench 204 is illustrated in FIG. 12(c). This extension can be referred to as an edge section of the trench element separation insulating material 208c. 
While not described in U.S. Pat. No. 5,981,356, a diffusion layer 209 (illustrated in FIG. 12(c)) is formed as a channel doped layer of a MOS transistor during the manufacturing of MOS transistors in succeeding processes. However, the diffusion layer 209 can become non-uniform in depth from the surface of the silicon substrate 201. This is due to the difference in the thickness of the pad oxide film 202a and the edge section of the trench element separation insulating material 208c. This difference in thickness causes a non-uniformity of the depth of impurity ions below the surface of the silicon substrate 201 after an ion implantation step is performed.
In this manner, a trench element separation region is formed in the trench 204 in a predetermined region of the silicon substrate 201 by filling the trench 204 with a liner oxide film 205 and a trench element separation insulating material 208c. 
In subsequent processes (not shown in the figure), a gate insulating film is formed. A gate electrode is then formed over the gate insulating film. In this manner, a MOS transistor is formed and isolated by used the trench element separation region.
As mentioned above, when using the conventional technique disclosed in JPA-049222, cavities can readily occur at the edges of the trench element separation insulating material. In a manufacturing process of semiconductor devices having trench element separation regions, it is extremely difficult to control the abovementioned cavities using this technique. As previously mentioned, this is because the silicon nitride film 103 can readily form an overhanging shape at the top section of the trench 104. It can be difficult to control this overhanging shape.
Furthermore, in the conventional technique disclosed in U.S. Pat. No. 5,981,356, the depth of the diffusion layer can become non-uniform, so that the impurity concentration of the channel doped layer of the MOS transistor becomes non-uniform. Thus, the dispersion of the threshold of the MOS transistor can become large. This dispersion becomes significant when the channel width of the MOS transistor becomes small.
In the conventional technique disclosed in U.S. Pat. No. 5,981,356, the occurance of the above-mentioned cavities may be theoretically avoided. However, if this technique is applied to a high volume semiconductor device production process, the above-mentioned cavities can occur and the depth of the diffusion layers can widely vary. This is due to the above-mentioned pullback process. Furthermore, the distance that the edge section 206 of the silicon nitride film is moved back from the top section of the trench 204 may not be controlled.
In light of the above discussion, it would be desirable to provide a semiconductor device which may have a trench element separation structure that can be precisely formed and a manufacturing method therefore.